Verification and Error Correction on High-Level Decision Diagrams.

      Аннотация: This book explores the theory of High-Level Decision Diagrams in application to formal verification and design error correction. We start with methods for synthesizing the diagrams for representing digital systems at higher behavioral, functional or register-transfer levels. The synthesized HLDDs can be used for high-level verification of digital systems. For this purpose, the HLDD model is appended by characteristic polynomials that canonically describe the graph structure of a diagram. These polynomials can be used for proving the equivalence between two HLDDs which have the same functionality but may have different structures. As soon as an error has been detected by the proposed approach, it must be localized and fixed. The described method is developed further to be applied to automated correction of design errors. We show how realistic design errors can be represented by the redirection-based fault model. The theoretical basis of the approach is presented with the key advantages being the ability to handle multiple errors as well as the fact that the error correction is not restricted by the input stimuli.

Ключевые слова: Formal Verification, Equivalence Checking, High-Level Decision Diagrams, Automated Error Correction, Formal Methods, Hardware verification