Energy Efficient Design Techniques On FPGA. Low power Design Goal with Capacitance Scaling, Thermal Aware, HSTL, SSTL & LVCMOS IO Standard and Frequency Scaling

      Аннотация: In this book we have designed 64 bit decoder, Internet of things (IoT)enable decoder, Energy Efficient Traffic Light Controller, Sensor based automatic barricades on public railway crossing, mobile charge sensor using LVCMOS IO Standard, Bio- Medical Wrist Watch, Unicode Reader of Greek, Latin and Sindhi, Digital Clock and FIR Filter using Verilog. And, we are using Design Goal, Capacitance Scaling, Frequency Scaling, Thermal Aware Design Approach, Clock Gating, Voltage Scaling, LVCMOS IO Standards, HSTL IO Standards, and SSTL IO Standards. We are using 28nm, 40nm Technology based latest Virtex-6, Kintex-7 and Artix-7 FPGA.We are using XPower Analyzer for Power Estimation and Xilinx for simulation of Hardware Description Language. In summary, we have covered more than 10 different Circuits and 10 different energy efficient technique that will help researcher, learner to learn these technique and apply these technique in their own design in order to make energy efficient design with Verilog.

Ключевые слова: Clock Gating, energy efficient, FPGA, frequency scaling, verilog, IO Standard, Design Goal, Thermal Aware, Capacitance Scaling