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Design Of High Speed and Low Power Multiplier.
В наличии
Местонахождение: Алматы | Состояние экземпляра: новый |
Бумажная
версия
версия
Автор: S. Gopalakrishnan and G. Sasi
ISBN: 9786139461349
Год издания: 2019
Формат книги: 60×90/16 (145×215 мм)
Количество страниц: 56
Издательство: LAP LAMBERT Academic Publishing
Цена: 23066 тг
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Аннотация: Power dissipation is recognized as a critical parameter in modern VLSI field. To produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary.The increasing speed and complexity of today’s designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. Multiplication is an important part of real-time digital signal processing (DSP) applications ranging from digital filtering to image processing.The Spurious Power Suppression Technique (SPST) uses a detection logic circuit to detect the effective data range of arithmetic units.
Ключевые слова: SPST, FPGA, HDL
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