A High Performance Low Power Universal Gate Implementation. In sub threshold region

      Аннотация: a new power reduction technique called Voltage Scaling Stacked Transistor (VS-STACK) has been presented. The proposed technique has been compared with some of the existing power reduction techniques. The result shows a colossal amount of reduction in power consumption for the 2input NOR gate. The power consumption is curtailed by 20% to 90%. Furthermore there is a tremendous improvement in the power delay product. Hence this technique can be used for high speed circuits. The circuit operates in subthreshold region which is suitable for applications that require extremely low power consumption

Ключевые слова: Universal Gates, CMOS Design, digital vlsi, Low Power, High Performance, Simulation